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M41T00S
Serial access real-time clock
Features

2.0 to 5.5 V clock operating voltage Counters for seconds, minutes, hours, day, date, month, year, and century Software clock calibration Automatic switchover and deselect circuitry (fixed reference) - VCC = 2.7 to 5.5 V 2.5V VPFD 2.7 V Serial interface supports I2C bus (400 kHz protocol) Low operating current of 300 A Oscillator stop detection Battery or SuperCapTM backup Operating temperature of -40 to 85C Ultra-low battery supply current of 1 A
8 1

SO8 (M) 8-pin SOIC
May 2008
Rev 4
1/26
www.st.com 1
Contents
M41T00S
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 2.3 2.4
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 3.2.2 3.2.3 3.2.4 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
M41T00S
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TIMEKEEPER(R) register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SO8 - 8-lead plastic small outline (150 mils body width), package mechanical data. . . . . 23 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
List of figures
M41T00S
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO8 - 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M41T00S
Description
1
Description
The M41T00S Serial Access TIMEKEEPER(R) SRAM is a low power serial RTC with a builtin 32.768 kHz oscillator (external crystal controlled). Eight bytes of the SRAM (see Table 2 on page 13) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two line, bidirectional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T00S has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the clock operations can be supplied by a small lithium button supply when a power failure occurs. The eight clock address locations contain the century, year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41T00S is supplied in an 8-pin SOIC.
Figure 1.
Logic diagram
VCC VBAT
XI XO M41T00S SCL SDA FT/OUT
VSS
AI09165
Table 1.
Signal names
XI XO FT/OUT SDA SCL VBAT VCC VSS Oscillator input Oscillator output Frequency test / output driver (open drain) Serial data input/output Serial clock input Battery supply voltage Supply voltage Ground
5/26
Description Figure 2. 8-pin SOIC (M) connections
M41T00S
XI XO VBAT VSS
1 8 7 2 3 M41T00S 6 4 5
VCC FT/OUT(1) SCL SDA
AI09166
1. Open drain output
Figure 3.
Block diagram
REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT RTC & CALIBRATION FREQUENCY TEST IC INTERFACE SCL WRITE PROTECT
2
CRYSTAL
32KHz OSCILLATOR
FT
SDA
FT/OUT
(1)
OUTPUT DRIVER
OUT
VCC
INTERNAL POWER
VBAT VSO VPFD
AI09168
COMPARE
1. Open drain output
6/26
M41T00S
Operation
2
Operation
The M41T00S clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1. 2. 3. 4. 5. 6. 7. 8. Seconds register Minutes register Century/hours register Day register Date register Month register Year register Calibration register
The M41T00S clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. Once VCC falls below the switchover voltage (VSO), the device automatically switches over to the battery and powers down into an ultra-low current mode of operation to preserve battery life. If VBAT is less than VPFD, the device power is switched from VCC to VBAT when VCC drops below VBAT. If VBAT is greater than VPFD, the device power is switched from VCC to VBAT when VCC drops below VPFD. Upon power-up, the device switches from battery to VCC at VSO. When VCC rises above VPFD, it will recognize the inputs. For more information on battery storage life refer to Application Note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
7/26
Operation
M41T00S
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 4. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
8/26
M41T00S Figure 5. Acknowledgement sequence
START SCL FROM MASTER 1 2 8
Operation
CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
2.2
READ mode
In this mode the master reads the M41T00S slave after setting the slave address (see Figure 7 on page 10). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge clock. The M41T00S slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 06h). The update will resume due to a stop condition or when the pointer increments to any non-clock address (07h).
Note:
This is true both in READ mode and WRITE mode. An alternate READ mode may also be implemented whereby the master reads the M41T00S slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 8 on page 10).
Figure 6.
Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
9/26
Operation Figure 7. READ mode sequence
START START R/W R/W
M41T00S
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
Figure 8.
Alternative READ mode sequence
START STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T00S slave receiver. Bus protocol is shown in Figure 9. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T00S slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 6 on page 9 and again after it has received the word address and each data byte.
10/26
R/W
NO ACK
ACK
M41T00S
Operation
2.4
Data retention mode
With valid VCC applied, the M41T00S can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the power input will be switched from the VCC pin to the battery when VCC falls below the battery backup switchover voltage (VSO). At this time the clock registers will be maintained by the attached battery supply. On power-up, when VCC returns to a nominal value, write protection continues for tREC. For a further, more detailed review of lifetime calculations, please see Application Note AN1012.
Figure 9.
WRITE mode sequence
START R/W STOP WORD ADDRESS (An) ACK ACK DATA n DATA n+1 DATA n+X P ACK ACK
AI00591
BUS ACTIVITY: MASTER
SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
ACK
11/26
Clock operation
M41T00S
3
Clock operation
The 8-byte register map (see Table 2) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of clock register 02h (century/hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 03h contain the Day (day of week). Registers 04h, 05h, and 06h contain the date (day of month), month and years. The eighth clock register is the calibration register (this is described in the clock calibration section). Bit D7 of register 00h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The seven clock registers may be read one byte at a time, or in a sequential block. The calibration register (address location 07h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
3.1
Clock registers
The M41T00S offers 8 internal registers which contain clock and calibration data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 06h). The update will resume either due to a stop condition or when the pointer increments to any non-clock address (07h). Clock registers store data in BCD. The calibration register stores data in binary format.
12/26
M41T00S Table 2.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h OUT ST OF CEB 0 0 0 CB 0 0 0 0 D6 D5 10 seconds 10 minutes 10 hours 0 10 date 10M 0 0 D4 D3 D2 D1 D0 Seconds Minutes Hours (24-hour format) Day of week Date: day of month Month Year Calibration
Clock operation TIMEKEEPER(R) register map
Function/range BCD format Seconds Minutes Century/hours Day Date Month Year Calibration 00-59 00-59 0-1/00-23 01-7 01-31 01-12 00-99
10 years FT S
Keys: 0 = must be set to '0' CB = century bit CEB = century enable bit FT = frequency test bit OF = oscillator fail bit OUT = output level S = sign bit ST = stop bit
3.2
Calibrating the clock
The M41T00S is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed 35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about 1.53 minutes per month (see Figure 10 on page 15). When the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature. The M41T00S design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 15. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the calibration register 07h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
13/26
Clock operation
M41T00S
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register (see Figure 11 on page 15). Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T00S may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in application note AN934, "TIMEKEEPER(R) calibration." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the FT/OUT pin. The pin will toggle at 512Hz, when the Stop bit (ST, D7 of 00h) is '0,' and the Frequency Test bit (FT, D6 of 07h) is '1.' Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the Calibration Byte does not affect the frequency test output frequency. The FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down.
14/26
M41T00S Figure 10. Crystal accuracy across temperature
Clock operation
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T - T )2 O F
2 2 K = -0.036 ppm/C 0.006 ppm/C
TO = 25C 5C
Temperature C
AI07888
Figure 11. Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
3.2.1
Century bit
Bits D7 and D6 of Clock Register 02h contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
3.2.2
Oscillator fail detection
If the Oscillator Fail bit (OF) is internally set to '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data.
15/26
Clock operation
M41T00S
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the oscillator. The following conditions can cause the OF bit to be set:

The first time power is applied (defaults to a '1' on power-up). The voltage present on VCC is insufficient to support oscillation. The ST bit is set to '1.' External interference of the crystal.
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF Bit to '0.'
3.2.3
Output driver pin
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the calibration register. In other words, when D7 (OUT Bit) and D6 (FT bit) of address location 07h are a '0,' then the FT/OUT pin will be driven low.
Note:
The FT/OUT pin is an open drain which requires an external pull-up resistor.
3.2.4
Preferred initial power-on default
Upon initial application of power to the device, the ST and FT bits are set to a '0' state, and the OF and OUT bits will be set to a '1.' All other register bits will initially power-on in a random state (see Table 3). Table 3. Preferred default values
Condition Initial power-up(1) Subsequent power-up (with battery
1. State of other control bits undefined. 2. UC = Unchanged
ST 0 backup)(2) UC
Out 1 UC
FT 0 0
OF 1 UC
16/26
M41T00S
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Sym TSTG VCC TSLD(1) VIO IO PD
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Supply voltage Lead solder temperature for 10 seconds Input or output voltages Output current Power dissipation Value -55 to 125 -0.3 to 7 260 -0.3 to VCC+0.3 20 1 Unit C V C V mA W
1. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution:
Negative undershoots below -0.3 volts are not allowed on any pin while in the battery backup mode
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DC and AC parameters
M41T00S
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 5. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M41T00S 2.7 to 5.5 V -40 to 85C 100 pF 50 ns 0.2VCC to 0.8 VCC 0.3VCC to 0.7 VCC
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC measurement I/O waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 6.
Symbol CIN COUT(3) tLP
Capacitance
Parameter(1)(2) Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1 MHz 3. Outputs deselected.
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M41T00S Table 7.
Sym ILI ILO ICC1
DC and AC parameters DC characteristics
Parameter Test condition(1) 0V VIN VCC 0V VOUT VCC Switch freq = 400 kHz SCL = 0Hz All Inputs VCC - 0.2 V VSS + 0.2 V -0.3 0.7VCC IOL = 3.0mA
(2)
Min
Typ
Max 1 1 300
Unit A A A
Input leakage current Output leakage current Supply current
ICC2
Supply current (standby)
70
A
VIL VIH VOL
Input low voltage Input high voltage Output low voltage Output low voltage (open drain)
0.3VCC VCC + 0.3 0.4 0.4 5.5 3.5(4) 0.6 1
V V V V V V A
IOL = 10mA FT/OUT 2.0 TA = 25C, VCC = 0 V Oscillator ON, VBAT = 3 V
Pull-up supply voltage (open drain) VBAT(3) Backup supply voltage IBAT Battery supply current
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 2.7 to 5.5 V (except where noted). 2. For FT/OUT pin (open drain). 3. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply. 4. For rechargeable backup, VBAT (max) may be considered to be VCC.
Table 8.
Sym fO RS CL
Crystal electrical characteristics
Parameter(1)(2) Resonant frequency Series resistance Load capacitance 12.5 Min Typ 32.768 Max 60(3) Units kHz k pF
1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T00S. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. For applications requiring backup supply operation below 2.5 V, RS (max) should be considered 40 k.
Figure 13. Power down/up mode AC waveforms
VCC VSO tPD SDA SCL DON'T CARE
AI00596
trec
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DC and AC parameters Table 9.
Symbol tPD trec
M41T00S
Power down/up AC characteristics
Parameter(1)(2) SCL and SDA at VIH before power down SCL and SDA at VIH after power up Min 0 10 Typ Max Unit nS S
1. VCC fall time should not exceed 5 mV/s. 2. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 2.7 to 5.5 V (except where noted).
Table 10.
Sym VPFD
Power down/up trip points DC characteristics
Parameter(1)(2) Min 2.5 Typ 2.6 25 VBAT < VPFD VBAT > VPFD VBAT VPFD 40 Max 2.7 Unit V mV V V mV
Power-fail deselect Hysteresis Battery backup switchover voltage (VCC < VBAT; VCC < VPFD) Hysteresis
VSO
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 2.7 to 5.5 V (except where noted).
Figure 14. Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
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M41T00S Table 11.
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA
DC and AC parameters AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns ns ns s ns s
tSU:DAT(2) Data setup time tHD:DAT tSU:STO tBUF Data hold time STOP condition setup time Time the bus must be free before a new transmission can start
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 2.7 to 5.5 V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
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Package mechanical information
M41T00S
6
Package mechanical information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 15. SO8 - 8-lead plastic small package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
Note:
Drawing is not to scale.
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M41T00S Table 12.
Symb Typ A A1 A2 B C D E E1 e h L L1 k N
ccc
Package mechanical information SO8 - 8-lead plastic small outline (150 mils body width), package mechanical data
mm Min Max 1.75 0.10 1.25 0.28 0.17 4.90 6.00 3.90 1.27 0.25 0.40 1.04 0 8
0.10
inches Typ Min Max 0.069 0.004 0.049 0.48 0.23 5.00 6.20 4.00 0.050 0.50 1.27 0.041 8 0 8
0.004
0.25
0.010
0.011 0.007 0.189 0.228 0.150
0.019 0.009 0.197 0.244 0.157
4.80 5.80 3.80
0.010 0.016
0.020 0.050
8
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Part numbering
M41T00S
7
Part numbering
Table 13.
Example:
Ordering information scheme
M41T 00S M 6 E
Device type M41T
Supply voltage and write protect voltage 00S = VCC = 2.7 to 5.5 V
Package M = SO8
Temperature range 6 = -40C to 85C
Shipping method E = ECOPACK(R) package, tubes F = ECOPACK(R) package, tape & reel
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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M41T00S
Revision history
8
Revision history
Table 14.
Date 10-Feb- 2004 20-Feb-2004 14-Apr-2004 05-May-2004 16-Jun-2004 13-Sep-2004 26-Nov-2004 14-May-2008
Document revision history
Revision 0.1 0.2 1.0 1.1 1.2 2.0 3.0 4 First draft Update characteristics (Table 9, 10, 5, 7, 13) Product promoted; reformatted; update characteristics, including Lead-free package information (Figure 4, 10; Table 4, 11, 13) Update DC characteristics (Table 7) Added package shipping (Table 13) Update maximum ratings (Table 4) Promote document; update characteristics; remove references to SOX18 package (cover page, Figure 4; Table 14) Reformatted document; updated Section 6, Figure 1, 15, Table 1, 4, 12, 13. Changes
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M41T00S
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